The present invention generally relates to an offsetting comparator device for use in tristate level determination of a differential signal, i.e., which of the three conditions xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9cZxe2x80x9d the signal assumes, for data communications purposes and so on. More particularly, the present invention relates to a technique of stabilizing the operation of the comparator device against a potential variation of the differential signal.
In a communications network, when the level of a differential signal should be determined as xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d or xe2x80x9cZxe2x80x9d, an offsetting comparator device is used to see if the potential difference of the differential signal has exceeded an offset voltage.
FIG. 19 illustrates a tristate level determination of a differential signal in compliance with the IEEE 1394 standard. As illustrated in FIG. 19, the level of the differential signal is determined as xe2x80x9c1xe2x80x9d when the potential difference thereof is larger than 165 mV; xe2x80x9c0xe2x80x9d when the difference is smaller than xe2x88x92165 mV; and xe2x80x9cZxe2x80x9d when the difference is in the range from xe2x88x92165 to 165 mV, both inclusive. Such a tristate level determination can be performed by connecting together a pair of comparator devices with an offset voltage of 165 mV and applying a voltage represented by the differential signal to the inverting input terminal of one of these comparator devices and to the non-inverting input terminal of the other.
FIG. 20 is a circuit diagram illustrating a conventional offsetting comparator device. In FIG. 20, a pair of p-channel transistors, which receive a differential input (C, D) with a fixed potential and supply currents I3 and I4, respectively, is connected in parallel to another pair of p-channel transistors, which receive a differential input (A, B) and supply currents I1 and I2, respectively. These currents I1, I2, I3 and I4 are combined at an output node so that a difference {(I2xe2x88x92I1)xe2x88x92(I4xe2x88x92I3)} between a sensed current corresponding to the potential difference represented by the differential input (A, B), i.e., (I2xe2x88x92I1), and an offset current, i.e., (I4xe2x88x92I3), is provided as output current to an external component. The potential difference of the differential input (A, B) when the sensed current (I2xe2x88x92I1) is canceled by the offset current (I4xe2x88x92I3) to bring the output current to zero is defined as xe2x80x9coffset voltagexe2x80x9d.
The known offsetting comparator device, however, has the following drawbacks.
FIG. 21 is a graph illustrating a relationship between an intermediate potential Vm of the differential input (A, B) and the magnitude of the current in the circuit shown in FIG. 20. In FIG. 21, the potential difference represented by the differential input (A, B) is supposed to be constant and the potential represented by the differential input (C, D) is fixed as described above. Thus, the magnitudes of the currents I3 and I4 are kept substantially constant irrespective of the potential represented by the differential input (A, B), and therefore the offset current (I4xe2x88x92I3) is also substantially constant as shown in FIG. 21.
However, even if the potential difference represented by the differential input (A, B) is constant, the magnitudes of the currents I1 and I2 are changeable with the potential variation. In Zone Za where the potential is larger than a potential obtained by subtracting a saturated drain-source voltage of the p-channel transistor from a supply potential, the magnitudes of the currents I1 and I2 are greatly variable with the potential represented by the differential input (A, B). In Zone Zb on the other hand, the transistors receiving the differential input (A, B) are not operable in their saturated regions anymore, but operate in a linear region. As a result, the sensitivity deteriorates, i.e., the sensed current (I2xe2x88x92I1) decreases. Thus, the offset voltage, i.e., the potential difference represented by the differential input (A, B) when the sensed current (I2xe2x88x92I1) is canceled by the offset current (I4xe2x88x92I3), is also greatly changeable with the potential represented by the differential input (A, B).
In general, the center potential of a differential signal is greatly changeable between a ground potential and a supply potential. Thus, an offsetting comparator device should always provide a constant offset voltage no matter where the center potential of the differential input is located within the range from the ground to supply potentials. Thus, if the offset voltage is greatly variable with the potential represented by the differential input as in Zones Za and Zb in FIG. 21, then serious problems are caused.
In addition, the characteristics of transistors included in the circuit are supposed to be non-changeable in the example illustrated in FIG. 21. Actually, though, the transistor characteristics might be affected by supply voltage, temperature or process conditions. Thus, the relationship between the offset current (I4-I3) and sensed current (I2-I1) is even more complicated, thus further lowering the stability of the offset voltage.
According to a conventional technique, a level shifter is provided as preceding stage of the comparator to reduce the range of the potential supplied to the comparator to at least about a half of the supply voltage (see U.S. Pat. No. 5,424,657, for example). In such a configuration, if the differential input potential is higher than the center potential of the supply voltage, then the input potential is provided to the comparator after having been lowered by the level shifter. Alternatively, if the differential input potential is lower than the center potential of the supply voltage, then the input potential is provided to the comparator as it is. As a result, the variation range of the differential input potential is in effect one half of the supply voltage.
According to this configuration, however, just of Zones Za and Zb shown in FIG. 21 can be eliminated and the problem cannot be solved radically. Also, if the differential input potential is changed by the level shifter, then the potential difference also increases albeit slightly, thus adversely affecting the stability of the offset voltage.
An object of the present invention is providing an offsetting comparator device that can obtain a constant offset voltage in spite of a potential variation of a differential signal.
Specifically, an offsetting comparator device according to the present invention determines whether or not a potential difference represented by a differential signal has exceeded an offset voltage. The device includes: a master comparator circuit, which receives the differential signal as differential input and supplies a sensed current corresponding to the potential difference represented by the differential input; and means for supplying an offset current. The device outputs a current representing a difference between the sensed and offset currents. The offset current supply means controls the magnitude of the offset current based on the potential level of the differential signal so as to stabilize the offset voltage.
According to the present invention, the magnitude of the offset current is controlled by the offset current supply means based on the potential level of the differential signal. Thus, even if the relationship between the potential difference represented by the differential input (or differential signal) and the sensed current has changed due to the potential variation of the differential signal, the magnitude of the offset current is controlled based on the potential represented by the differential signal. Accordingly, the offset voltage, which is a potential difference represented by the differential input when the sensed current is canceled by the offset current, does not change. As a result, a constant offset voltage can be obtained even if the potential represented by the differential signal has changed.
In one embodiment of the present invention, the offset current supply means preferably includes: a reference differential voltage generator, which receives an intermediate potential represented by the differential signal as input and outputs a reference differential voltage corresponding to the intermediate potential; and a slave comparator circuit, which receives the reference differential voltage as another differential input and outputs a current corresponding to the potential difference as the offset current. The slave comparator circuit has the same configuration as the master comparator circuit.
In this particular embodiment, each of the master and slave comparator circuits preferably receives the associated differential input at respective parallel gates of p- and n-channel transistors.
In an alternate embodiment, each of the master and slave comparator circuits may include: a first pair of transistors of one conductivity type, which receive the differential input; a second pair of transistors of the other conductivity type, which receive the differential input; and a third pair of transistors of the one conductivity type, through which a current, corresponding to the current flowing through the second pair of transistors, flows by way of a current mirror. Each said comparator circuit outputs a sum of differential currents of the first and third pairs of transistors. A current is supplied from a common constant current source to the first and third pairs of transistors.
In still another embodiment, the reference differential voltage generator may include: a potential generator, which includes a resistor and generates both potentials represented by the reference differential voltage based on the intermediate potential and a voltage drop caused by the resistor; and a current controller for controlling the amount of current flowing through the resistor such that the voltage drop caused by the resistor becomes constant.
In this particular embodiment, the potential generator preferably includes an operational amplifier, which receives the intermediate potential as one of the inputs. The resistor preferably connects the other input of the operational amplifier to the output thereof. The output of the operational amplifier is preferably output as one of the potentials represented by the reference differential voltage.
In an alternate embodiment, the potential generator may include an operational amplifier, which receives the intermediate potential as one of the inputs. The resistor may include: a first resistor connecting the other input of the operational amplifier to the output thereof; and a second resistor connected in series to the first resistor. The potential generator preferably outputs potentials at both terminals of the first and second resistors as the potentials represented by the reference differential voltage.
In still another embodiment, the potential generator may include first and second resistors connected in series to each other. The intermediate potential is applied to a connection node of the resistors. The potential generator preferably outputs potentials at both terminals of the first and second resistors as the potentials represented by the reference differential voltage.
In still another embodiment, the comparator device may further include means for delaying the differential signal for a predetermined time, which is provided on an input end of the master comparator circuit.
Another offsetting comparator device according to the present invention determines whether or not a potential difference represented by a differential signal has exceeded an offset voltage. The device includes: a master comparator circuit, which receives the differential signal as differential input and supplies a sensed current corresponding to the potential difference represented by the differential input; and a slave comparator circuit for supplying an offset current. The device outputs a current representing a difference between the sensed and offset currents. Each of the master and slave comparator circuits includes: a first pair of transistors of one conductivity type, which receive the differential input; a second pair of transistors of the other conductivity type, which receive the differential input; and a third pair of transistors of the one conductivity type, through which a current, corresponding to the current flowing through the second pair of transistors, flows by way of a current mirror. Each said comparator circuit outputs a sum of differential currents of the first and third pairs of transistors. A current is supplied from a common constant current source to the first and third pairs of transistors.
A comparator circuit according to the present invention supplies a current corresponding to a potential difference represented by a differential input. The circuit includes: a first pair of transistors of one conductivity type, which receive the differential input; a second pair of transistors of the other conductivity type, which receive the differential input; and a third pair of transistors of the one conductivity type, through which a current, corresponding to the current flowing through the second pair of transistors, flows by way of a current mirror. The circuit outputs a sum of differential currents of the first and third pairs of transistors. A current is supplied from a common constant current source to the first and third pairs of transistors.